Semiconductor devices, such as metal oxide semiconductor field effect transistors (“MOSFETs”), junction field effect transistors (“JFETs”), and double diffused metal-oxide semiconductor (DMOS) transistors etc. are widely used in various electronic products. Generally, to protect a gate oxide of such a semiconductor device from being damaged by electro-static discharge (“ESD”), an ESD protection module is coupled between a gate and a source of the semiconductor device. The ESD protection module is configured to provide a conduction path between the source and the gate of the semiconductor device, once a gate to source voltage of the semiconductor device caused by ESD exceeds an ESD threshold voltage, so that a large extra energy due to ESD can be discharged promptly through the conduction path. The ESD protection module is usually desired to be integrated into the semiconductor device that it is intended to protect for reducing the size and manufacturing cost of the semiconductor device.
FIG. 1A illustrates schematically a cross-sectional view of a typical semiconductor device 10 having a power transistor such as MOSFET 11 and an ESD protection module 12 integrated together. FIG. 1B illustrates a top plan view of the semiconductor device 10. The cross-sectional view in FIG. 1A can be considered as being cut from the cut line AA′ in FIG. 1B. As shown in FIG. 1A, the semiconductor device 10 is formed on a substrate 13 having an active area 101 and a termination area 102 (also referring to FIG. 1B). The MOSFET 11 is formed in the active area 101 of the substrate 13 and may comprise a gate region 15, a source region 16 and a drain region, wherein the drain region comprises a portion of the substrate 13 near the bottom surface S of the substrate 13. In FIG. 1A, the gate region 15 is illustrated as a trenched gate region electrically coupled to a gate metal 17 through a trenched gate runner 15T and a first interlayer via 221. The trenched gate runner 15T has a same structure as the trenched gate region 15 but with wider trench width to facilitate formation of the via 221. The electrical connection of the gate region 15 to the trenched gate runner 15T is illustrated by a dotted line in FIG. 1A. The source region 16 is electrically coupled to a source metal 18 through a second interlayer via 222.
The ESD protection module 12 is formed on a thick isolation layer 21 atop the termination area 102 of the substrate 13, wherein the thick isolation layer 21 electrically isolates the ESD protection module 12 from the substrate 13. Typically, the ESD protection module 12 may comprise a group of PN diodes formed by depositing a polysilicon layer 19 atop the thick isolation layer 21, and subsequently doping the polysilicon layer 19 with P type and N type dopants. The ESD protection module 12 (i.e. the group of PN diodes formed by the alternately arranged P type doped regions and N type doped regions) is electrically coupled between the source metal 18 and the gate metal 17 to protect a gate oxide of gate region 15 from being damaged by a large extra energy due to ESD. The source metal 18 and the gate metal 17 can be electrically coupled to the ESD protection module 12 respectively through a third interlayer via 223 and a fourth interlayer via 224.
Now referring to FIG. 1B, the gate metal 17 is formed around the source metal 18 and is normally disposed above the termination area 102 of the substrate 13. The gate metal 17 has a gate metal pad 171 and a gate metal runner 172. Turning back to FIG. 1A, an interlayer dielectric (ILD) layer 20 is normally formed between the metal layer (including the gate metal 17 and the source metal 18) and the substrate 13 and the ESD protection module 12 to isolate the gate metal 17 and the source metal 18 from the substrate 13 and the polysilicon layer 19 of the ESD protection module 12. The first interlayer via 221, the second interlayer via 222, the third interlayer via 223 and the fourth interlayer via 224 are formed through the ILD layer 20 and filled with conductive material. However, the first interlayer via 221 is generally formed only under the gate metal runner 172 but not under the gate metal pad 171 since the ESD protection module 12 is disposed under the gate metal pad 171, which makes it rather difficult to form an interlayer via from the gate metal pad 171 through the ILD layer 20, the polysilicon layer 19 and the thick isolation layer 21 to reach the substrate 13. Therefore, the gate metal pad 171 can not be electrically coupled to the gate region 15 through structures like the first interlayer via 221 and the trenched gate runner 15T, which adversely affects the electrical conductivity between the gate region 15 and the gate metal 17.
Moreover, since the ESD protection module 12 (including the polysilicon layer 19 and the thick isolation layer 21) has a great thickness (measured in the direction perpendicular with the bottom surface S of the substrate 13), there exists a large transition step 23 from the top surface of the MOSFET 11 to the top surface of the ESD protection module 12. This large difference in height between the top surface of the MOSFET 11 and the top surface of the ESD protection module 12 renders a problem for forming the interlayer vias 221, 222, 223 and 224. It is generally desired to form these interlayer vias in a same step to simplify manufacturing process and save cost. However, for the semiconductor device 10 in FIG. 1A, the third interlayer via 223 and the fourth interlayer via 224 which are located on a higher position (at top of the transition step 23) can hardly be formed in the same step for forming the first interlayer via 221 and the second interlayer via 222 which are located on a lower position (at foot of the transition step 23). For example, when the interlayer vias 221, 222, 223 and 224 are formed by etching the ILD layer 20 with the shield of a patterned photoresist layer in a same step, patterning of the photoresist layer may be greatly affected by the large transition step 23 under a given focal depth. If the patterns defining the first and the second interlayer vias 221 and 222 are focused, the patterns defining the third and the fourth interlayer vias 223 and 224 may be out of focus. Thus, the third and the fourth interlayer vias 223 and 224 may not be precisely formed as required or even can not be opened, especially when the required critically dimension of the vias is small.